| 摘要 |
<p>A cache coherence system and method for use in a multiprocessor computer system having a plurality of processors, a memory and an interconnect network connecting the plurality of processors to the memory. The memory includes a plurality of lines and a cache coherence directory structure having a plurality of directory structure entries. Each of the directory structure entries is associated with one of the plurality of lines and each directory structure entry includes processor pointer information, expressed as a set of bit vectors, indicating the processors that have cached copies of lines in memory.</p> |
