| 摘要 |
The present invention relates to a pipeline microprocessor (MP1, MP2) comprising a program counter (PC), means (MUX, ADD) for the incrementation of the program counter (PC), instruction decoding means (PREDEC, DEC1, DEC2, DEC3) comprising means (PREDEC) to decode a conditional jump instruction (JMPc) of the program counter, a bank of registers (REGBANK), a computation unit (ALU) comprising a first output (S1) to deliver a result and a second output (S2) to deliver status bits (C, N, P, Z) of the result. According to the invention, the computation unit (ALU) and the means (PREDEC, DEC3) for decoding the conditional jump instruction (JMPc) are laid out in two neighboring pipeline stages (ST1, ST2), and the means (PREDEC) for decoding the conditional jump instruction (JMPc) are connected to the second output (S2) of the computation unit (ALU). |
