| 摘要 |
<p>PROBLEM TO BE SOLVED: To provide a flash memory which suppresses the variations of a voltage applied to each of memory cells at erasing and the current flowing in each memory cell. SOLUTION: The memory comprises a memory cell array divided in blocks each having source lines 16, 17 per word line 21 with a low resistance 14 connected in series to each source line, select gate provided to apply a high voltage to each source line at the time of the sequential erase, and circuit for controlling the select gate, thereby limiting the variation of the erasing voltage applied to each source line and the current flowing on each source line.</p> |
