| 摘要 |
PROBLEM TO BE SOLVED: To reduce the additional capacitance of a clock transfer line and realize a low power consumption and a high speed transfer. SOLUTION: A single phase clock CK0 is inputted to each C-MOS analog switch 16 whose switching control is practiced in accordance with the output pulse of each OR gate 18 which receives two inputs, i.e., the input pulse of a transfer stage one stage before and the output pulse of a transfer stage of itself. In accordance with the single phase clock CK0 supplied selectively through the C-MOS analog switch 16, clocks CK and CKX whose phases are opposite to each other are generated by a clock generating circuit 14 and supplied to clocked inverters 11 and 12 to practice the transfer operations of the respective transfer stages only if necessary. |
