| 摘要 |
<p>A sensing circuit (10) for sensing the multiple states of a selected memory cell (12a, ..., 12n) of a floating gate memory device is disclosed. The sensing circuit (10) has a first voltage amplifier (20) which generates a first output voltage (22), and a plurality of current amplifiers (42a, ..., 42n) which receive the first output voltage (22) and generate a plurality of first output currents in response thereto. The sensing circuit (10) also comprises a dummy cell (14), a second voltage amplifier (24) connected thereto for generating a second output voltage. A second current amplifier (26) receives the second output voltage and generates a plurality of second output currents in response thereto. Each of a plurality of inverters (28a, ..., 28n) receives one of the first and one of the second output currents, and generates an output (S1, ..., Sn). The output (S1, ..., Sn) of the plurality of inverters (28a, ..., 28n) are supplied to a decoder (50) to generate a decoded signal (K) representative of the plurality of states of the selected memory cell (12a, ..., 12n).</p> |
