| 摘要 |
<p>Boundary scan integrated circuits are provided with a plurality of new registers (56, 61, 62, 65, 67) between two dedicated pins, Test Data In (TDI) (16) and Test Data Out (TDO) (18) pins. The registers include an address register (56) and a plurality of test data registers (61, 62, 65, 66, 67) which are addressed by the address register using address instructions in the (IR) (23). Instructions for the addressable registers may be steered to the correct register with an ADDLOAD instructions placed in the (IR) followed by an address-dependent register active between the (TDI) and (TDO) pins. Any instruction from a set of address-dependent instructions may be steered to any register handling address dependent instructions allowing a small number of instructions to be used in a large number of addressable data registers. Non-addressable registers, such as the boundary scan registers (54), use address-independent instructions.</p> |
