| 摘要 |
The data exchange device between data processing units (1), includes processors (4), that are interconnected by an external multi-wired exchange bus (2), common to all the devices and whose sharing is controlled by a referee (3). Each unit includes a memory (5, 6, 15) whose data is conserved, at least temporarily, at set addresses which can be written to or read from on demand. The assembly formed by the units has an exchange memory spread amongst the units (1) common to all the units and accessible by any via the exchange bus (2). The device includes intermediate storage (10, 11) in each unit, between the exchange memory (15) and the exchange bus (2); this is made up of rapid access buffer memory to which the processor (4) of the unit accedes to the timing rhythm that controls it and to which the other units accede to the timing rhythm controlling the exchange bus. Each unit generates a first timing signal (CLK) designed to be transmitted by the exchange bus to the other units, and each gather a second timing signal (CLKD) from the exchange bus, so as to produce a third timing signal designed to enable local use of the data. |
