| 摘要 |
A non-volatile semiconductor memory device of the present invention includes a plurality of memory cell array blocks on a single integrated circuit, each of the blocks including non-volatile memory transistors capable of electrically writing, erasing, and reading information, arranged in a matrix. Control gates of the transistors in each identical row are commonly connected to form word lines, drains of the transistors in each identical column are commonly connected to form bit lines, and sources of all of the transistors are commonly connected. Each of the blocks further includes a bit line selection circuit which selectively connects the plurality of bit lines to a data bus in accordance with a signal value of a predetermined portion of an input address signal, and an output circuit for selectively outputting a predetermined voltage to the commonly connected sources at a time of writing, erasing, and reading information. The plurality of word lines of each of the blocks are connected to the corresponding word lines in an adjacent block through a plurality of switching transistors provided between the blocks, two word line selection circuits are provided which output a predetermined word line selection signal in accordance with a signal value of the other predetermined portion of the input address signal. The word lines of predetermined two blocks among the plurality of blocks are respectively connected to the corresponding word line selection circuits, and each of the bit line selection circuits connects the bit line selected in accordance with the signal value of the predetermined portion of the input address signal alternatively to either of the two data buses. <IMAGE> |
