| 摘要 |
A sense amplifier senses a small voltage differential across true and complementary digit lines in a dynamic random access memory (DRAM) integrated circuit. The sensed voltage is further separated and amplified into full logic levels. Activating the P-sense amplifier before the N-sense amplifier speeds sensing. The P-sense amplifier control signal is capacitively coupled to each of the true and complementary digit lines. The P-sense amplifier further increases the more positive digit line to the power supply voltage Vcc. The other digit line is at a voltage more positive than its equilibration voltage, speeding conduction of a subsequently activated N-sense amplifier, particularly for low values of Vcc, in which the threshold voltages of the NFETs in the N-sense amplifier are close to the equilibration voltage. Capacitor elements need not be added to the sense amplifier layout.
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