| 摘要 |
A circuit that determines the remainder of a modulo 2 polynomial division in just one clock cycle. Specifically, each term of the remainder is determined in parallel with each other term of the remainder. The circuit includes a network of XOR devices to determine H(X)=P(X) mod G(X), where P(X) is a first binary polynomial, of a form: amXm+am-1Xm-130 . . . +a0, where a={0,1} and X={0,1}; G(X) is a second binary polynomial, of a form: anXn+an-1Xn-1+. . . +a0, where a={0,1} and X={0,1}, and m>n; and H(X) is a third binary polynomial, of a form: bpXp+bp-1Xp-1+ . . . +0. The configuration of the network of XOR devices is determined by reducing terms of the first binary polynomial to have only terms having less than the degree of the second binary polynomial. Then, for each term of the third binary polynomial (i.e., the remainder), it is determined which reduced terms of the first binary polynomial affect it. From this determination, the configuration of sub-networks of XOR devices is determined.
|
