发明名称 Test mode for multifunction PCI device
摘要 In a multifunction PCI device containing identical backend functions or other large, redundant functional blocks, a single backend function is selected as a primary function while in test mode. All backend I/O channels are then simultaneously tested in parallel, with the same data and control signals from a PCI local bus being driven to all backend channels during the same test clock cycle. A single backend channel is designated as the primary for providing requisite handshaking signals during output to the backend I/O channels. Input data from each backend channel is received in parallel and compared, with miscompares being flagged to allow testing of the input data path from the respective backend I/O channel. Only signals from the primary backend I/O channel are designated for transmission to the PCI local bus. Signals from the remaining backend channels are received in parallel with and compared to the signals from the primary channel, and miscompare flags are generated for any discrepancies identified. The resulting parallel testing of all backend I/O channels within the multifunction device reduces the number of test vectors needed to achieve fault grade goals.
申请公布号 US5905744(A) 申请公布日期 1999.05.18
申请号 US19970940866 申请日期 1997.09.30
申请人 LSI LOGIC CORPORATION 发明人 REISE, BRIAN G.;SMITH, PAUL J.
分类号 G06F11/273;(IPC1-7):G06H7/02 主分类号 G06F11/273
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