Demodulator for a pulse width modulated signal and method

摘要

A demodulator for a pulse width modulated signal comprises a counter arranged to count in one direction when the PWM signal is "high" and in the opposite direction when the PWM signal is "low" to arrive at a count representative of a duty cycle. As a result, a value representative of the duty ratio of the PWM signal can be obtained from the up/down counter. In a further embodiment, the up/down counter is clocked by the output of a frequency multiplier, the output of the frequency multiplier having a frequency determined by the pulse width modulated signal frequency multiplied by a predetermined factor. The value of the duty ratio of the PWM signal can then be found regardless of the frequency of the PWM signal.