发明名称 Dynamic memory
摘要 In a dynamic RAM having a memory cell array in which a dynamic memory cell is arranged at an intersection between a word line and one of a pair of bit lines, a select level signal corresponding to a supply voltage and an unselect level signal corresponding to a negative potential lower than circuit ground potential are supplied to the word line. A signal of a memory cell read to the pair of bit lines by a sense amplifier that operates on the circuit ground potential and an internal voltage formed by dropping the supply voltage by an amount equivalent to the threshold voltage of the address select MOSFET is amplified. The dynamic RAM has an oscillator that receives the supply voltage and circuit ground potential and a circuit that receives an oscillation pulse generated by the oscillator to generate the negative potential.
申请公布号 US5905685(A) 申请公布日期 1999.05.18
申请号 US19970951734 申请日期 1997.10.15
申请人 HITACHI, LTD.;HITACHI ULSI ENGINEERING CORP. 发明人 NAKAMURA, MASAYUKI;HASEGAWA, MASATOSHI;NARUI, SEIJI;TANAKA, YOUSUKE;MIYATAKE, SHINICHI;KUBOUCHI, SHUICHI;KAJIGAYA, KAZUHIKO
分类号 G11C11/407;G11C11/401;G11C11/4074;G11C11/408;G11C11/409;H01L21/8242;H01L27/108;(IPC1-7):G11C7/00 主分类号 G11C11/407
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