发明名称 Method for forming multilevel interconnection of semiconductor device
摘要 A method for forming a multilevel interconnection of a semiconductor device of the present invention includes the steps of forming a first wiring layer by depositing a metallic film containing aluminum on an insulating film of a substrate and patterning the metallic film, forming an interlayer insulating film on the entire surface of the substrate to cover the wiring layer from the upper side, forming a connection hole reaching to the first wiring layer at a predetermined position of the interlayer insulating film, selectively depositing aluminum onto an interior of the connection hole at a volume fraction of 100% or more by CVD to fill the interior of the connection hole, flattening the entire upper surface of the interlayer insulating film including the connection hole filled with aluminum by a polishing process, washing the entire surface flattened by the polishing process, and depositing the metallic film containing aluminum at a predetermined position of the upper surface of the flattened and washed interlayer insulating film and patterning the metallic film, thereby forming a second wiring layer connected to the first wiring layer through aluminum filled in the connection hole.
申请公布号 US5904557(A) 申请公布日期 1999.05.18
申请号 US19970794936 申请日期 1997.02.04
申请人 TOKYO ELECTRON LIMITED 发明人 KOMIYA, TAKAYUKI;KAWANO, YUMIKO
分类号 H01L21/3205;H01L21/304;H01L21/3105;H01L21/768;H01L23/522;H01L23/532;(IPC1-7):H01L21/28 主分类号 H01L21/3205
代理机构 代理人
主权项
地址