发明名称 Digital processing system for binary addition/subtraction
摘要 A digital processing system for binary addition/subtraction includes an adder for adding two binary data respectively expressed by two's complements to output the addition result, an overflow carry detector for outputting an overflow carry signal indicating an overflow carry of the addition result, an exclusive OR gate for outputting the sign bit of the addition result of the adder with or without inversion, and a register for storing the output from the exclusive OR gate.
申请公布号 US5905662(A) 申请公布日期 1999.05.18
申请号 US19970927210 申请日期 1997.09.11
申请人 KABUSHIKI KAISHA TOSHIBA 发明人 SHIRAISHI, MIKIO
分类号 G06F7/00;G06F7/50;G06F7/505;(IPC1-7):G06F7/38 主分类号 G06F7/00
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