发明名称 Computer with a cache controller and cache memory with a priority table and priority levels
摘要 A computer system according to the present invention comprises a processor, a priority table for storing an address indicative of the original location of each of data items to be read by the processor, and a priority corresponding to the frequency of access by the processor to read each of the data items, a cache memory for storing, in units of cache blocks, part of the data items to be read by the processor, the cache memory having a tag which stores an address and a priority corresponding to each of the data items, and a controller including means for obtaining, when a cache miss has occurred, a priority corresponding to data whose reading is requested by the processor, by referring to the priority table and using an address included in the data-reading request of the processor, and means for comparing the obtained priority with a priority of data stored in a predetermined cache block in the cache memory, thereby to determine whether or not data replacement should be performed in the predetermined cache block.
申请公布号 US5906000(A) 申请公布日期 1999.05.18
申请号 US19970802840 申请日期 1997.02.18
申请人 KABUSHIKI KAISHA TOSHIBA 发明人 ABE, YUICHI;MATOBA, TSUKASA
分类号 G06F12/08;G06F12/12;(IPC1-7):G06F12/00 主分类号 G06F12/08
代理机构 代理人
主权项
地址