发明名称 Hierarchical routing method to be implemented in a layout system for a semiconductor integrated circuit and medium on which the hierarchical routing program is stored
摘要 A hierarchical routing method is implemented in a layout system for a semiconductor integrated circuit which has a repetitive circuit portion. The hierarchical routing method lays out circuit elements for the repetitive circuit portion with the repetitive circuit portion structured hierarchically, expands the layout for the hierarchically-structured repetitive circuit portion in a separate independent database, extracts information of connections from the expanded layout for the repetitive circuit portion, and then carries out routing. Therefore, a semiconductor integrated circuit having a repetitive circuit portion can be designed in a short period of time while excellent properties are ensured for the semiconductor integrated circuit.
申请公布号 US5905669(A) 申请公布日期 1999.05.18
申请号 US19970940005 申请日期 1997.09.29
申请人 FUJITSU LIMITED 发明人 HORITA, KEISUKE
分类号 H01L21/822;G06F17/50;H01L21/82;H01L27/04;(IPC1-7):G11C5/02 主分类号 H01L21/822
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