| 摘要 |
PURPOSE:To expand a practical frequency-locking range by driving a PLL circuit so that a frequency difference between the maximum repeating frequency of a data string signal and the frequency of a demodulation clock is included with the frequency locking range of the PLL circuit. CONSTITUTION:At the time of judging an unlocked state by a lock detecting means, output signals of a frequency detector 160 are time-dividedly multiplexed with output signals of a phase comparator 110 to form a phase-compared output 121. Namely at the time of judging the impossibility of data demodulation, a multiplexing means 120 time-dividedly multiplexes the output signals 111, 112 of the comparator 110 with the output signals 161, 162 of the detector 160 and outputs the signal 121. The operation is repeated until the frequency fPCK of a demodulation clock 152 is included with the frequency locking range (capture range) of the PLL circuit and reflected to the output signals 161, 162 of the detector 160, i.e., both of the output signals 161, 162 are steadily turned to a logical level '0'. |
