| 摘要 |
A system console (30) is enabled to read registers from memory boards 12 and 14 and to set registers within the memory boards which control the disabling of one or more memory arrays (16-22). The information read from the memory boards is indicative at least of which of the memory arrays has malfunctioned. The registers are within a memory logic array (40), one of which is disposed upon each of the memory boards (12) and (14) and also upon a memory controlling unit (26), the memory logic arrays being coupled together by a bit serial scan bus 41. In a preferred embodiment of the invention the memory logic arrays 40 are comprised of a highly integrated gate array semiconductor device, each of which is identical. Each memory logic array is provided with a base address input (46) from a preceding memory logic array and computes a base address for a subsequent memory logic array. A memory logic array which has a portion of an associated memory disabled automatically determines a revised base address for the subsequent memory logic array, thereby initiating the automatic reallocation of memory board base addresses of all subsequent memory boards. |
