| 摘要 |
A bus analyzer used in a multiprocessor computer system having a common system bus includes a bus tester for storing test data used to test the system bus and internal data paths of the bus analyzer. The test data is output to the system bus to initiate a testing operation. A trace memory sequentially receives and stores the test data provided from the system bus. A memory controller controls the trace memory to store the test data received from the system bus in response to a trace signal and interrupt storage of the test data in response to a trigger signal. A test controller generates the trace signal and the trigger signal output to the memory controller, reads the test data stored in the trace memory, and compares the test data read from the trace memory with the test data stored in the bus tester. The bus analyzer of the present invention is capable of independently testing its own internal data paths without signals provided from an external source or additional apparatus. |
