摘要 |
A system and method for optimizing the amount of time it takes for a requestor (device) (540, 320) to receive data (230) from a memory storage unit (110) in a multi-requestor bus environment. The present invention provides a unidirectional response signal (740), referred to as an early warning signal (740), sent from a memory storage unit (110) to a device (540, 320), sometime after that device (540, 320) has executed a fetch request for data (230), to alert the device (540, 320) that the data (230) if forthcoming. This early warning signal (740) allows the device (540, 320) to arbitrate for the data bus (520, 340) so that when the data (230) arrives, the device (540, 320) will have exclusive ownership of the data bus (520, 340) to accept the data (230) immediately. The present invention comprises a main memory (110), a cache memory (510), one or more processor modules (120), one or more I/O modules (320), and an early warning bus (710). The cache memory (510) is connected to the main memory (110) via an interface bus (130). The processor modules (120) are connected to the cache memory (510) via a processor interface bus (520). The I/O modules (320) are connected to the main memory (110) via an I/O interface bus (340). Both the processor modules (120) and the I/O modules (320) include means for requesting a data unit from the main memory. The early warning bus (710) is connected between the main memory (110), the cache memory (510), and the I/O module (320).
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申请人 |
UNISYS CORPORATION |
发明人 |
BAUMAN, MITCHELL, A.;SCHIBINGER, JOSEPH, S.;KALVESTRAND, DONALD, R.;MORRISSEY, DOUGLAS, E. |