发明名称 |
SYNCHRONOUS CONTENT ADDRESSABLE MEMORY WITH SINGLE CYCLE OPERATION |
摘要 |
A content address memory (CAM) device. The CAM device is a synchronous device that may perform all of the following operations all in one clock cycle: (1) receive comparand data from a comparand bus; (2) receive an instruction from an instruction bus instructing the CAM device to compare the comparand data with a first group of CAM cells in a CAM array; (3) perform the comparison of the comparand data with the first group of CAM cells; (4) generate a match address for a location in the CAM array that stores data matching the comparand data; (5) access data stored in a second group of the CAM cells in the CAM array, wherein the second group of CAM cells may store data associated with the matched location; and (6) output to an output bus the match address, the data stored in the second group of CAM cells, and/or status information corresponding to the matched address or the second group of CAM cells. The status information may include a match flag, multiple match flag, full flag, skip bit, empty bit, or a device identification for the CAM device. The CAM array may also include ternary CAM cells that are individually maskable so as to effectively store either a logic one, logic zero, or a don't care state for compare operations.
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申请公布号 |
WO9923663(A1) |
申请公布日期 |
1999.05.14 |
申请号 |
WO1998US21853 |
申请日期 |
1998.10.14 |
申请人 |
NETLOGIC MICROSYSTEMS, INC.;SRINIVASAN, VARADARAJAN;NATARAJ, BINDIGANAVALE, S.;KHANNA, SANDEEP |
发明人 |
SRINIVASAN, VARADARAJAN;NATARAJ, BINDIGANAVALE, S.;KHANNA, SANDEEP |
分类号 |
G11C15/00;G11C15/04;(IPC1-7):G11C15/04 |
主分类号 |
G11C15/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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