| 摘要 |
<p>The invention concerns a microprocessor (MP) comprising means for decoding (DEC1) a compact instruction (BMV) for concatenating at least one bit (bi) of a first binary word (W1) with at least one bit of a second binary word (W2), and means (REGBANK, MUX, BSHIFT) for processing said instruction in one clock cycle. The invention provides the advantage of ensuring a rapid concatenation operation and is particularly applicable to smart cards.</p> |
