A DIRECTORY-BASED CACHE COHERENCY SYSTEM

摘要

A system uses a directory-based memory (910) and a plurality of third level non-inclusive caches (920) to implement a coherent caching system (900). In the caching system (900), a main memory (910) is interfaced to a plurality of non-inclusive, third level caches (920). Each third level cache (920) is interfaced to two pairs of processors (930). Each pair of processors (930) shares a common bus (940). Each processor (930) is also interfaced to a first level cache (970) and a second level cache (970). The caching system (900) maintains coherence for data (915) in the main memory (910) using a directory-based protocol. The caching system (900) maintains coherence for data in each of the third level caches (920) (referred to as cache lines (925)) using a directory-based protocol as well.