发明名称 |
Method and circuit for regulating the length of an ATD pulse signal |
摘要 |
<p>The invention relates to a method and a circuit for regulating a pulse synchronization signal (ATD) for the memory cell read phase in semiconductor integrated electronic memory devices. The pulse signal (ATD) is generated upon detection of a change in logic state of at least one of a plurality of address input terminals of the memory cells, so as to also generate an equalization signal (SAEQ) to a sense amplifier. The SAEQ pulse is blocked (STOP) upon the row voltage reaching a predetermined sufficient value to provide reliable reading. Advantageously, the pulse blocking is produced by a logic signal (STOP) activated upon a predetermined voltage value being exceeded during the overboost phase of the addressed memory row. <IMAGE></p> |
申请公布号 |
EP0915476(A1) |
申请公布日期 |
1999.05.12 |
申请号 |
EP19970830573 |
申请日期 |
1997.11.05 |
申请人 |
STMICROELECTRONICS S.R.L. |
发明人 |
CAMPARDO, GIOVANNI;MICHELONI, RINO;ZAMMATTIO, MATTEO;FERRARIO, DONATO |
分类号 |
G11C11/41;G11C8/18;(IPC1-7):G11C8/00;G11C7/00 |
主分类号 |
G11C11/41 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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