The B mode processor (54) has a signal envelope detector providing input to a logarithmic data compression stage (48a) and to a low pass filter (52a). The outputs are fed to a signal edge shaping stage (50) and to a further data compression stage (48b). Signals are combined in an adaptive weighting circuit and the output is directed to an anti-aliasing filter (52b).
申请公布号
DE19850505(A1)
申请公布日期
1999.05.12
申请号
DE19981050505
申请日期
1998.11.03
申请人
GENERAL ELECTRIC CO., SCHENECTADY, N.Y., US
发明人
MO, LARRY Y. L., WAUKESHA, WIS., US;MILLER, STEVEN C., WAUKESKA, WIS., US