发明名称 Logical circuit capable of uniformizing output delays for different inputs
摘要 In a logical circuit including a logical unit connected to first through N-th input terminals and to first and second power supply lines (2, 3) for carrying out a logical operation on first through N-th input signals supplied to the first through the N-th input terminals, where N represents an integer greater than one, the logical unit has first through fourth transistor arrays (TA1-TA4), each of which is connected between the first and the second power supply lines. Each of the first through the fourth transistor arrays has transistors, equal in number to the input terminals, connected in series. Each of the transistors is of an MIS (metal insulator semiconductor) type and has a gate. Each transistor of each transistor array of the first through the fourth transistor arrays has the gate which is connected to any one of the first through the N-th input terminals so that the number of the transistors connected between one of the first and the second power supply lines and the transistors having the gates connected to a particular input terminal of the first through the N-th input terminals is equal to the number of the transistors connected between the one of the first and the second power supply lines and the transistors having the gates connected to each of the first through the N-th input terminals except the particular input terminal. <IMAGE>
申请公布号 EP0817388(A3) 申请公布日期 1999.05.12
申请号 EP19970110667 申请日期 1997.06.30
申请人 NEC CORPORATION 发明人 OHASHI, MASAYUKI
分类号 H01L21/822;H01L27/02;H01L27/04;H01L27/088;H03K19/003;H03K19/0944;H03K19/0948;H03K19/20 主分类号 H01L21/822
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