CLOCK SYNCHRONIZATION DEVICE, CLOCK SYNCHRONIZATION METHOD, COMMUNICATION EQUIPMENT AND COMMUNICATION METHOD USING THE METHOD

摘要

PROBLEM TO BE SOLVED: To obtain clocks in phase with plural modules having reduced number of wires to suppress the production of noise. SOLUTION: A master module 1 frequency-divides a basic clock with high frequency produced by a master module basic clock generating section 5 for producing a PLL reference clock 3 and various clocks and to provide an output of a PLL reference clock 3 with low frequency and a reset pulse 4 produced by a reset pulse generating section 7. A slave module frequency-divides a basic clock with high frequency generated by a slave module basic clock generating section 8 by various clock generating sections 9 in a slave module 2 and generates various clocks whose phase is adjusted, based on the PLL reference clock 3. A reset pulse 4 is used to reset the slave module various clock generating section 9 for each prescribed period, so as to synchronize the phase of the various clocks in the master module with the phase of the various clocks in the slave module.