发明名称 Method of forming a narrow polysilicon gate with i-line lithography
摘要 A new method for forming a feature having a feature size of one half the resolution of the photolithography process by adjusting the etching conditions is achieved. A capping oxide layer is deposited overlying the feature layer. A first layer of photoresist is patterned using a photolithography process to provide a first photomask having a first feature size. The oxide layer is etched vertically through no more than half of its thickness and the photomask and oxide layer are etched horizontally to provide a first oxide mask having a second feature size one half the width of the first feature size. The first photomask is removed. A second photoresist layer is patterned to provide a second photomask for forming the second feature wherein the second photomask has a first feature size and is shifted horizontally by twice the desired feature size from the first photomask. The oxide layer is etched vertically through no more than half of its thickness and the photomask and oxide layer are etched horizontally to provide a second oxide mask having a second feature size one half the width of the first feature size. All of the capping oxide layer is removed except for the first and second oxide masks. The second photomask is removed. The feature layer is etched through where it is not covered by the first and second oxide masks to form the first and second features having the second line width of one half the resolution of the photolithography process in the manufacture of an integrated circuit device.
申请公布号 US5902133(A) 申请公布日期 1999.05.11
申请号 US19970910268 申请日期 1997.08.13
申请人 VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATION 发明人 LINLIU, KUNG
分类号 H01L21/033;H01L21/28;H01L21/3213;(IPC1-7):H01L21/302 主分类号 H01L21/033
代理机构 代理人
主权项
地址