| 摘要 |
PROBLEM TO BE SOLVED: To improve the extract efficiency of a clock signal without complicating the configuration of a circuit for recovering the clock signal. SOLUTION: A signal whose transmission speed is one over an even number in a reception equalization signal is extracted through an extract filter 21 and a broadband amplifier 22 and a frequency multiplier circuit 23 multiplies the signal by a multiple of even numbers. The multiplied resulting signal whose transmission speed is equal to that of the received signal is given to a timing filter (dielectric resonator) 24 having a band-pass characteristic whose Q is enhanced by sufficiently narrowing the pass-band width, and a clock signal is extracted. The clock signal is given to a limiter amplifier 25, where the signal is amplified into a rectangular wave signal to obtain a recovered clock signal. |
