| 摘要 |
PROBLEM TO BE SOLVED: To provide a frame synchronization system capable of shortening the time until establishment synchronization. SOLUTION: A 1.5 M logic path termination section 3 is made up of a 1.5 M logic path bit extract section 44 that extracts an Fs bit which is a frame synchronization bit from an ST bit in 16-bit included in a signal of a 6.3 Mb/s, a frame synchronization pattern detection section 8 that detects a frame synchronization pattern from the extracted bit string for providing an output of the detected bit string to a PN pattern generator, a PN pattern generator 5 that generates a collation pattern, a collation section 6 that takes matching between the reception bit string and the collation pattern, and a synchronization establishment discrimination section 7 that discriminates synchronization establishment, based on the collation result. |
