| 摘要 |
A high capacitance DRAM structure is provided for a capacitor over bit line DRAM structure. A planarized dielectric layer is provided over the transfer FETs and the bit line contact of a COB structure. A silicon nitride layer is provided over the planarized dielectric layer to serve as an etch stop for a subsequent wet etching process. A first sacrificial oxide layer is deposited over the silicon nitride etch stop layer and then contacts are opened through the various dielectric layers to the appropriate source/drain regions of the transfer FETs. A first polysilicon layer is deposited within the capacitor contact openings and over the first sacrificial oxide layer. A second sacrificial oxide layer is provided and openings are formed in the second sacrificial oxide layer substantially centered over the capacitor contacts. A second polysilicon layer is provided over the second sacrificial oxide layer and in contact with the first polysilicon layer. The lateral extent of polysilicon fins is defined using conventional photolithography and etching on the second polysilicon layer, the second sacrificial oxide layer and the first polysilicon layer in sequence. A wet etch is used to remove the remaining portions of the second sacrificial oxide layer and the first sacrificial oxide layer. The surfaces of the resulting polysilicon fins may be covered with hemispherical grained polysilicon to further increase their surface area. A capacitor dielectric is provided over the fins and an upper capacitor electrode is formed to complete the charge storage capacitor.
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