发明名称 |
Method for optimizing element sizes in a semiconductor device |
摘要 |
A slack time, based on a required and actual delay time, is calculated for each node in a circuit (302). For each element in the circuit, a sensitivity (304) and a figure of merit (306) is calculated. A variance is determined for the calculated figure of merits (308). The circuit element having the smallest absolute figure or merit is optimized when the variance is smaller than a predefined threshold (310, 312).
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申请公布号 |
US5903471(A) |
申请公布日期 |
1999.05.11 |
申请号 |
US19970805862 |
申请日期 |
1997.03.03 |
申请人 |
MOTOROLA, INC. |
发明人 |
PULLELA, SATYAMURTHY;EDWARDS, TIMOTHY J.;NORTON, JOSEPH;DHARCHOUDHURY, ABHIJIT;BLAAUW, DAVID |
分类号 |
H01L21/82;G06F17/50;(IPC1-7):G06F19/00 |
主分类号 |
H01L21/82 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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