| 摘要 |
A computer-implemented method for aiding in the design of an integrated circuit (IC) floorplan. The method comprises receiving a netlist, physical layout information, and timing constraints of the IC and performing timing analysis of the signal paths of the IC. The user selects the set of nets to by analyzed. The timing analysis comprises calculating net delays as a function of the length of the signal paths. The timing analysis further comprises calculating slack times by subtracting from the clock cycle time of the IC the sum of the driven at timing constraint, the needed by timing constraint, and the net delay. Paths which have a slack time greater than a slack failure value are passing nets and paths which have a slack time greater than a slack failure value are failing nets. The slack failure value is user-specifiable and defaults to zero. The method further comprises displaying in a spreadsheet the timing constraints, net delays, and slack times for each path selected, thus providing the designer with complex multi-dimensional feedback. The feedback for each path in the spreadsheet is accompanied by a hyperlink button, which the designer selects in order to graphically display the path on a graphical view of the floorplan. Thus the designer is enabled to relate the non-graphical timing information to a graphical display of the paths and apply his or her intuitive knowledge to make necessary changes to the floorplan. The timing information is further summarily displayed in a histogram, thus providing visual feedback regarding the timing quality of the floorplan. The method provides means for the designer to display failing paths, passing paths, all paths, and paths skipped in timing analysis due to the absence of timing constraints.
|
