发明名称 |
System to improve trapping of I/O instructions in a peripheral component interconnect bus computer system and method therefor |
摘要 |
A system for trapping I/O instructions. The system is comprised of at least one peripheral controller for receiving a plurality of I/O instructions and for initiating trapping of an un-executable I/O instruction by issuing a target abort signal when the peripheral controller senses a power off condition in a peripheral device. A system controller is coupled to the at least one peripheral controller for receiving the target abort signal from the at least one peripheral controller and for sequentially: issuing a system management interrupt (SMI) signal; counting a predetermined time period to allow recognition of the SMI signal; and issuing a cycle completion signal after counting the predetermined time period. A CPU is coupled to the system controller for issuing a plurality of I/O instructions and for receiving the SMI signal and the cycle completion signal from the system controller.
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申请公布号 |
US5903773(A) |
申请公布日期 |
1999.05.11 |
申请号 |
US19960704281 |
申请日期 |
1996.08.28 |
申请人 |
VLSI TECHNOLOGY, INC. |
发明人 |
RICHARDSON, NICHOLAS JULIAN;DAVIS, BARRY;HICOK, GARY |
分类号 |
G06F11/07;(IPC1-7):G06F11/30 |
主分类号 |
G06F11/07 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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