| 摘要 |
A device for the digital performance of a binary division according to a non-restoring type of division method chiefly comprises a circuit for the detection of null partial remainders during the division. Advantageously, combinational circuits are designed to compute a correction bit to correct the quotient in a single instruction. Finally, there is advantageously provided a circuit for the computation, at each division step, of the complemented quotient bit for the next division step and a multiplexer for the introduction, at the next step, of the reverse of this complemented quotient bit on the least significant position of the quotient. Application to signal processors.
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