发明名称 |
Power reduction for UART applications in standby mode |
摘要 |
A power reduction system for a UART system having a controllable oscillator for producing free-running clock signals. A controlled clock synchronizer having an output terminal is coupled to the oscillator and responsive to both a first control signal thereto and application of the free-running clock signals thereto to provide synchronized pulses and is responsive to both a second control signal different from the first control signal thereto and application of the free-running clock signals thereto to cease production of the synchronized pulses at the output terminal. A UART core controls the oscillator and the clock synchronizer and is operated under control of clock signals from the clock synchronizer. The controllable oscillator includes an inverter having a feedback circuit thereacross including a switch responsive to the third control signal to cause the oscillator to cease oscillation. The synchronizer includes a bistable circuit responsive to the first and second control signals and a gate responsive to the bistable circuit and the clock signals for controlling the status of the synchronized pulses at the output terminal.
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申请公布号 |
US5903601(A) |
申请公布日期 |
1999.05.11 |
申请号 |
US19960768249 |
申请日期 |
1996.12.17 |
申请人 |
TEXAS INSTRUMENTS INCORPORATED |
发明人 |
ELNASHAR, KHODOR S.;YAZDANI, MAHMOUD M.;LEWIS, CLARENCE D. |
分类号 |
G06F13/38;(IPC1-7):G06F1/32 |
主分类号 |
G06F13/38 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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