| 摘要 |
An extended 4-input 2-output addition block (1a) is provided, along with 4-input 2-output addition blocks (2a to 2c), in the first stage of a tree circuit. Further, 4-input 2-output addition blocks (2d and 2e) are provided in the second stage and a 4-input 2-output addition block (2f) is provided in the third stage. Input signals of the addition blocks in the same stage arrive at the same time and the number of logical stages in a critical path of the tree circuit is reduced. Thus, parallel operation of the circuit is improved, to thereby ensure higher-speed operation of a multiplier.
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