发明名称 Outer buried contact region connecting drain region to inner buried contact region
摘要 An FET semiconductor substrate includes source/drain regions with an outer buried contact region overlapping the drain region, a gate oxide layer, and a polysilicon layer over the gate oxide layer. An inner buried contact opening through the polysilicon and the gate oxide layer reaches down to the substrate over the outer buried contact region. An inner buried contact region, within the outer buried contact region, is self-aligned with the buried contact opening. A second polysilicon layer formed over the gate oxide layer reaches down through the buried contact opening into contact with the inner buried contact region. An interconnect and a gate electrode are formed from the polysilicon layers. Source/drain regions are self-aligned with the gate electrode and whereas the drain region is spaced from the inner buried contact region, the outer buried contact region interconnects the drain region with the inner buried contact region.
申请公布号 US5903035(A) 申请公布日期 1999.05.11
申请号 US19970938798 申请日期 1997.09.26
申请人 TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. 发明人 WU, YI-HUANG;CHEN, DER-CHEN
分类号 H01L21/8244;H01L27/11;(IPC1-7):H01L29/76 主分类号 H01L21/8244
代理机构 代理人
主权项
地址
您可能感兴趣的专利