PARALLEL PROCESSING PATTERN GENERATION SYSTEM FOR AN INTEGRATED CIRCUIT TESTER

摘要

A parallel processing pattern generation system for an integrated circuit tester includes two pattern memories (PM2, PM3), a main pattern generator (PG1), and two auxiliary pattern generators (PG2, PG3). Each pattern memory may receive and store data patterns from a host computer (24) before the test. All three pattern generators may produce data pattern sequences in a variety of ways by executing separately stored algorithmic programs. The pattern sequences generated by each of the two auxiliary pattern generators separately address the two pattern memories so that either one or both of the two pattern memories may read out pattern data during a test. The main pattern generator includes a routing circuit (30) for receiving as inputs a portion of the pattern data generated by the main pattern generator itself and the pattern data read out of the two pattern memories. The routing circuit, controlled by another portion of the pattern data produced by the main pattern generator, selects from among its inputs on a bit-by-bit, cycle-by-cycle basis to provide pattern data for controlling tester activities during each cycle of a test.