| 摘要 |
A fully CMOS SRAM cell has two V-shaped active regions formed symmetrically on either side of a well trench and spaced from two further active regions (44, 45) formed symmetrically alongside one another, two gate lines intersecting the V-shaped active regions and the well trench and another gate line intersects the further active regions. A fully CMOS SRAM cell with pMOS and nMOS transistors comprises (a) a well trench (41) for separating a substrate (40) into n-well (NW) and p-well (PW) regions; (b) first and second V-shaped active regions (42, 43) lying symmetrically to one another on either side of the well trench (41); (c) third and fourth active regions (44, 45) formed symmetrically alongside one another and spaced from the second active region (43); (d) second and third gate lines (32, 33) formed successively and intersecting the first active region (42), the well trench (41) and the second active region (43); and (e) a first gate line (31) which intersects the third and fourth active regions (44, 45). An Independent claim is also included for production of the above SRAM cell.
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