METHOD FOR CALCULATING PROPAGATION DELAY TIME OF LOGIC CIRCUIT

摘要

A method for calculating the propagation delay time of a logic circuit accurately even when the capacitance of the input terminal of the cell of the logic circuit varies depending upon the waveform dullness of the impressed signal, unlike the conventional propagation delay time calculating method wherein the delay time is calculated by considering that the capacitance of the input terminal of the cell has a fixed value. In the present method, however, the delay time is calculated by taking the capacitance variation of the input terminal caused by the waveform dullness of the input signal into consideration by storing the capacitance of the input terminal as a function of waveform dullness in a delay library. Also disclosed is a logic circuit synthesizing method in which the delay time of each candidate logic circuit is considered to be the object of comparison as a criterion for selecting the optimum solution out of the candidate solutions of a plurality of logic circuits which realize a desired logical function.