| 摘要 |
<p>A low power bank architecture implemented in memory access circuitry is disclosed. The bank architecture includes a bank circuit that has a bank core (204) integrated with a pair of bitlines and a bank interface circuit (430, 432) that is coupled to the pair of bitlines. The bank architecture further includes a global data bus pair that is configured to communicate a less than full rail voltage swing. The global data bus pair is coupled to the bank interface circuit (430, 432) of the bank circuit that is designed to convert the less than full rail voltage swing into an up to about full rail voltage swing that is communicated to the pair of bitlines. The bank circuit is configured to be replicated once for each of the pair of bitlines in a memory core having an array of bank cores. By communicating memory access signals, such as differential write data, at a less than full rail voltage over the global data bus pair, a substantial amount of power is saved, which provides excellent power savings for many electronic device applications.</p> |
