| 摘要 |
<p>A fractional frequency synthesizer (100) includes a symmetrical divider (165) having an output frequency signal (135) fractionalized based on half cycles of its input frequency signal (130). The divider (165) is provided with a divisor (145) that varies based on half cycles of the output signal. Preferably, the divider (165) operates to selectively add or subtract an increment, corresponding to one half cycle of the input frequency signal (130), to a half cycle of the output frequency signal (135).</p> |
