发明名称 |
Timing phase synchronization detecting circuit and demodulator |
摘要 |
<p>A demodulator is made compact, and with a simple circuit arrangement, and also having a better bit error rate characteristic. A timing phase synchronization detecting circuit 219 judges any one of the following two conditions based upon baseband phase data 202, i.e., an UNLOCK (timing phase asynchronous) condition, and a LOCK (timing phase synchronous) condition. Based upon the judgement result of the timing phase synchronization detecting circuit 219, in a timing recovering means 221, a frequency range of a PLL (phase synchronization loop) is variable, whereas the number of data entered within 1 symbol time is variable in a frequency synchronizing means 222 and a carrier recovering means 223. A data demodulating means 224 outputs demodulation data 206 in response to baseband phase data 202 and a recovery carrier signal 205.</p> |
申请公布号 |
EP0913963(A2) |
申请公布日期 |
1999.05.06 |
申请号 |
EP19980120086 |
申请日期 |
1998.10.23 |
申请人 |
MITSUBISHI DENKI KABUSHIKI KAISHA |
发明人 |
OKUBO, SEIJI;FUJIMURA, AKINORI;MIYAKE, MAKOTO |
分类号 |
H04L27/22;H03L7/095;H03L7/107;H04L7/00;H04L7/033;H04L7/04;H04L27/00;H04L27/233;(IPC1-7):H04L7/033 |
主分类号 |
H04L27/22 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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