A loading arrangement for the input stage of a source coupled logic gate, which loading arrangement comprises a loading element having at least one resistive element and at least one voltage limiting element connected in parallel with one another. There is also disclosed a loading arrangement comprising resistive and voltage limiting elements connected in parallel. <IMAGE>
申请公布号
EP0810734(A3)
申请公布日期
1999.05.06
申请号
EP19970108708
申请日期
1997.05.30
申请人
BUSHEHRI, EBRAHIM;BRATOV, VLADIMAR;STAROSELSKI, VICTOR I.
发明人
BUSHEHRI, EBRAHIM;BRATOV, VLADIMAR;STAROSELSKI, VICTOR I.