| 摘要 |
A typical structure for the data processing device of the present invention comprises a memory cell array part having a plurality of memory cells for storing data, first and second address terminals for receiving address signals, a first controller for receiving a first read signal and outputting a first read control signal, a second controller for receiving a second read signal and outputting a second read control signal, a first latch circuit for holding data outputted from a memory cell corresponding to an address signal provided at the first address terminal in response to the first read control signal and a second latch circuit for holding data outputted from a memory cell corresponding to the address signal provided at the second address terminal in response to the second read control signal.
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