| 摘要 |
The invention presents a method and apparatus for forming a restricted model from a system model to reduce the computational resources required to formally verify the system design, without substantially reducing the ability to test all system model functions, or properties. In general, the restricted model is formed by restricting the range of assumable values of system model variables and system model inputs to a restricted set of values, based on the values assumed by the system model variables and system model inputs during a partial search of the system model. The restricted model can then be fully searched by a conventional verification tool to identify system design errors. Advantageously, the restricted model requires less computational resources during a fall search than the original system model.
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