发明名称 |
Redundancy architecture and method for block write access cycles permitting defective memory line replacement |
摘要 |
An invention is disclosed which implements bit line redundancy in a memory module, such as a dynamic random access memory (DRAM), in accordance with a block write operation. The block write operation is commonly used in dual port RAMs, sometimes referred to as video random access memories (VRAM). Specifically, a block write operation allows a plurality of bits of data to be written to a plurality of adjacent bit lines defined by a column address. The precise combination of adjacent bit lines selected by the column address is designated by an address mask. The invention provides a memory module with a redundant bit decoder that incorporates an address masking function into the redundant bit decoder during block write operations and also bypasses a masking function during normal read and write operations. This redundant bit decoder allows a single redundant bit line to replace any single defective bit line of the selected group of block write bit lines. It eliminates the need for replacing all the selected bit lines and, thereby, saves silicon area and maximizes the utilization of available redundant bit elements. |
申请公布号 |
US5901093(A) |
申请公布日期 |
1999.05.04 |
申请号 |
US19950464044 |
申请日期 |
1995.06.05 |
申请人 |
INTERNATIONAL BUSINESS MACHINES CORPORATION |
发明人 |
HILTEBEITEL, NATHAN RAFAEL;TAMLYN, ROBERT;TOMASHOT, STEVEN WILLIAM;WYCKOFF, THOMAS WALTER |
分类号 |
G11C11/401;G11C29/00;G11C29/04;(IPC1-7):G11C7/00 |
主分类号 |
G11C11/401 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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