| 摘要 |
A horizontal synchronization signal generating circuit self-generates a horizontal synchronization signal if an actual horizontal synchronization signal fails to be detected in a composite video signal. Each time an edge-detection circuit detects an actual horizontal synchronization pulse, a counter and decoder are reset. An actual horizontal synchronization signal has a period of 63.5 mu s. If the edge detection circuit fails to detect the actual horizontal synchronization signal, then the decoder outputs a self-generated horizontal synchronization signal at 64 mu s and a selector circuit disables the edge detection circuit for approximately 35 mu s. In contrast, if the edge-detection circuit detects an actual horizontal synchronization signal, the decoder is reset before it can output the self-generated signal and the selector disables the edge detection circuit for approximately 60 mu s. Accordingly, a period of 35 mu s exists during which an edge-detecting signal is disabled after a horizontal synchronizing output produced by self-generation has been outputted. The disabling period allows detection of horizontal synchronizing inputs when narrow pulse signals are lost during vertical synchronous periods, and allows immediate extraction of the horizontal synchronizing inputs regardless of the difference of the odd/even fields and allows outputting of the corresponding horizontal synchronizing output.
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